The processor will be targeted at four-socket servers, says Shannon Poulin, Xeon platform director at Intel. Each physical core will be able to run two threads simultaneously, giving the chip 64 virtual processing cores on servers.

Intel’s CEO Paul Otellini has described Nehalem-EX as the company’s fastest processor to date. The chip maker announced the processor last year, and said it would release the chip in the first half of this year, but did not provide an exact release date.

Poulin declined to provide the clock speed of the chips. However, the company has said it will include 24MB of cache and 2.3 billion transistors.

Intel is targeting the chip at high-end systems running data-intensive applications such as databases. IBM has said when the chip is released it would implement Nehalem-EX chips in the company’s System x EX5 servers.

The chip will be made using the 45-nanometer process and be based on the Nehalem microarchitecture, which integrates the memory controller and improves system speed by cutting data bottlenecks that plagued Intel’s earlier chips.

Intel is also including new technologies like MCA recovery error correction, which could make servers more fault tolerant and provide greater uptime, he says. The processor will be able to detect system errors originating in the CPU or system memory and correct them by working with the operating system. Some of these technologies have been adapted from Intel’s high-end Itanium processors, which are based on a separate chip architecture and go into fault-tolerant systems.

The new processor will also contain separate buffered memory chips, which can store data temporarily alongside the main memory for faster task execution.

Intel will also offer four memory channels per processor, Poulin says. That will put it on par with AMDs’ twelve-core Opteron server processors, code-named Magny-Cours, which also offer four memory channels per processor. More channels provide more memory bandwidth to run programs faster.

AMD has started shipping Magny-Cours processors, with Intel’s Nehalem-EX set to intensify the battle between the rivals, as both companies reach out to claim benchmark crowns, says Nathan Brookwood, principal analyst at Insight 64. Intel will build large amounts of cache inside Nehalem-EX that could help the processor deliver faster performance, but AMD’s Magny Cours has more physical cores per chip.

Benchmark results could vary depending on the type of task assigned, but performance is just one part of the story, he says. Nehalem-EX could reach out to new markets with additional features like fault-tolerance, Brookwood says. It could tread into territory of high-end servers dominated by Intel’s Itanium and chips based on RISC (reduced instruction set computer) architecture, which includes IBM’s Power and Sun’s Sparc processors.

Last year, when the Nehalem EX was first announced, Boyd Davis, Intel’s general manager for server platforms in the Intel marketing department, said: “This is going after a market that was limited to being served by RISC architecture”, and “We think Nehalem-EX will represent a pretty significant opportunity on the overall server and hardware market”.
But AMD could hold an advantage over Intel’s Nehalem-EX in pricing. Intel could charge a premium for Nehalem-EX chips, while AMD chips could deliver better bang-for-buck per core with Magny-Cours, Brookwood says.

Intel’s Poulin also says the company would release its next-generation Xeon server processors based on the Westmere microarchitecture later this month. The processors will be targeted at two-socket servers, Poulin says. Chips for four-socket servers will be released next year.

Intel says server chips based on Westmere will contain up to six cores. The company last month said the six-core chip contained 1.17 billion transistors and 12MB of cache. The six-core chips will deliver improved performance and power savings compared to earlier quad-core chips, according to the company.

The Westmere-EP chips will fall under the Xeon product line and will be made using the 32-nanometer process. The last refresh for server chips was in March last year, when the company announced a range of Xeon 5500 series and 3500 series chips based on the Nehalem architecture. The chips were made using the 45-nm process.

www.computerworld.co.nz

“To lead the entire semiconductor industry with the most advanced process technology is a phenomenal feat for Intel and Micron, and we look forward to further pushing the scaling limits,” said Brian Shirley, vice president of Micron’s memory group. “This production technology will enable significant benefits to our customers through higher density media solutions.”

“Through our continued investment in IMFT, we’re delivering leadership technology and manufacturing that enable the most cost-effective and reliable NAND memory,” said Tom Rampone, vice president and general manager, Intel NAND Solutions Group. “This will help speed the adoption of solid-state drive solutions for computing.”

So what does this mean for consumers? Basically, the shrink to 25nm reduces the dies size of the NAND flash chips, which enables higher densities, and hence the chip count within products can be reduced by up to 50% when compared to the previous process generation. It allows for smaller, yet higher density designs at lower costs. For example, a particular SSD may be able to be produced using only 16 chips versus 32. Solid State Drives will feature larger maximum capacities while prices of current options will be driven further down. We were told to expect performance to be on par with 34nm products, though there are the obvious intrinsic benefits of a die geometry shrink from a performance standpoint.

Of course, there will be a number of products based on this technology over time. The first one will be the industry’s first monolithic 8GB NAND device. At a die size of 167mm², it is twice the capacity of their highest density 34nm part in roughly the same footprint. It is small enough to fit through the hole in the middle of a compact disc, but is able to store more than 10 times the data capacity of a CD. In roughly the same real estate, SSD makers will now be able to provide double the capacity as the previous generation.

IMFT is on track to begin production of this device and expects to start shipping in the second quarter of this year. Consumers can expect products featuring 25nm flash memory towards the end of 2010.

Micron and Intel are also supporters of the Open NAND Flash Interface (ONFI). ONFI is a consortium of tech companies working to develop open standards for NAND memory and supporting devices. The formation of the group was initially announced at the Intel Developer Forum in 2006 and began the effort to standardize the low level interface to NAND flash chips that are on the market today. One of the main motivations for this is to make it easier to switch between chips from different manufacturers, which allows faster development of NAND-based products and lower prices through broader competition among manufacturers. Besides Intel and Micron, the ONFI consortium is led by several prominent manufactures of NAND such as Hynix, SanDisk, and Sony.

The 8GB NAND device shown above supports the ONFI 2.2 interface standard, delivering up to 200MB/s of throughput bandwidth. Both Intel and Micron have been pleased with it and feel it is very much in tune to what they have driven in the DRAM world, using standard synchronous interfaces to increase speed. This is critical when SSD manufacturers rely on high speed communication between chips.

In January 2006, Micron and Intel formed IM Flash Technologies, LLC. IMFT combines the technology, assets, and industry experience of the two companies to create NAND flash memory. Jointly investing over $2 billion dollars, they opened up a semiconductor fabrication plant in Lehi, Utah which currently operates 24 hours a day, 7 days a week. This fab employs about two thousand people.

The central area of the fab is the clean room, where the environment is controlled and air is scrubbed to eliminate dust down to micrometer size and no more than 10 particles per cubic meter levels. Before entering the fabrication areas, we put on clean room suits also known as bunny suits. These garments covered all parts of the body with the exception of eyes and the nose. Once inside, the lack of people working inside the fab was surprising. It was explained that most of the people we saw were technicians conducting preventive maintenance and ensuring the equipment operated within specifications. What the images are unable to show is the bustling movement of machinery occurring overhead and along the walls of this fully automated fab, carrying materials to the various stations within the plant.

www.hothardware.com

What makes oFono different?

oFono aims to provide an easy to use interface that can be used to create rich telephony applications without requiring one to have a deep understanding of the underlying technology and its limitations. To accomplish this, oFono provides language-independent D-Bus API that is extremely easy to use without generated bindings or other ‘messy’ steps typically required to use an IPC based API.

The API follows the following four basic principles:

• Consistent
• Minimal
• Easy to use
• Complete

Consistent

The API should be consistent. Functionality in oFono is broken up into Interfaces, each with well-defined set of Properties. Each interface has a GetProperties() and a SetProperty() method which is used to accomplish majority of the tasks. Naming conventions are also strictly enforced. This means that once you’re comfortable using one Interface, you should be able to easily orient yourself to use others.

Minimal

The API should be minimal; there shouldn’t be more than one way of accomplishing a task as this leads to confusion and API bloat. We also aim to maintain API compatibility whenever possible, from the very beginning. This means that oFono APIs wil generally focus on the most important use-cases. Other features will be carefully considered before being included in the APIs.

Complete

At the same time, the APIs must be rich and complete enough to enable the creation of feature complete mobile phones. Thus, APIs for all aspects of telephony are planned, incudling but not limited to Voice calls, SMS, Cell Broadcast, Supplementary Services and SIM Phonebooks.

Easy to use

oFono aims to make writing telephony applications as easy as possible. Thus oFono will take care of the core logic, including things necessary for standards compliance. This will allow application writers to focus on what they should be doing: presentation aspects and funky animated UIs.

www.ofono.org

OCZ’s Neutrino netbook barebone features 10″ screen and, according to the company, allows end-user to install memory, hard disk drive or solid state drive based on demand and preferences. It is unknown whether OCZ will provide an option to choose between factory-installed single-core and dual-core Intel Atom processor, but that would be a tremendously useful feature for enthusiasts. It is also not clear whether OCZ Neutrino is based on the rather outdate Intel 945 GSE core-logic platform with DirectX 9-class graphics or utilizes the newest Intel GN40 chipset with DirectX 10-supporting graphics core.

The new DIY initiative from OCZ proves that netbook category has become rather popular on the market and even suppliers of advanced components sold at premium price believe that their customers may be interested in customizable netbooks.

“Proving that good things come in small packages, the Neutrino packs a huge punch for on-the-go traveling, educational, home use, or any user looking for a physically light computer but heavy on the useful applications and functionality,” OCZ said in a statement.

OCZ Neutrino barebone is expected to emerge in the U.S. sometime in Q2 2009.

www.xbitlabs.com

Products based on the new microarchitecture will deliver high performance and energy efficiency. This “best of both worlds” approach is expected to extend Intel’s processor leadership in future mobile, desktop and server market segments.

“The Core name is and will be our flagship PC processor brand going forward,” said Sean Maloney, Intel Corporation executive vice president and general manager, Sales and Marketing Group. “Expect Intel to focus even more marketing resources around that name and the Core i7 products starting now.”

Intel Core i7

The Intel Core processor brand name has gained broad awareness, preference, and market momentum over the past several years. The Intel Core name remains the logical choice for Intel’s latest family of processors. The Intel Core i7 processor brand logo will be available for high-performance desktop PCs with a separate black logo for Intel’s highest-end “Extreme Edition.” Intel will include processor model numbers to differentiate each chip.

Initial products based on this microarchitecture are expected to be in production in the fourth quarter of this year. These processors will feature Intel® Hyper-Threading Technology, also known as simultaneous multi-threading, and are capable of handling eight software “threads” on four processor cores.

www.intel.com